The present invention relates to a technique for use in the fabrication of a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique that is effective when applied to a wafer-level electrical test of a semiconductor integrated circuit device.
A probe test is one of the techniques employed for the inspection of semiconductor integrated circuit devices. It includes a function test for confirming whether a wafer functions to specification or not, or a test for judging whether the wafer is non-defective or defective by measuring its DC operating characteristics and its AC operating characteristics.
In recent years, a probe test of semiconductor integrated circuit devices tends to be carried out while they are in the stage of a semiconductor wafer (which will hereinafter simply be called a “wafer”) to satisfy the requirements for shipment of the devices in the wafer form (differentiation of products), KGD (Known Good Die) (improvement in the yield of MCP (Multi-Chip Package)) and reduction in the total cost.
For example, there is a prober that is used for a wafer-level probe test, which comprises a multilayer film having a plurality of contact terminals disposed in a predetermined region on the probing side, a lead-out wire to be electrically connected to each contact terminal and a ground layer opposite to the lead-out wire with an insulating layer sandwiched therebetween, and the film is attached to a holding member to eliminate slack in the region. Further, this prober has a constitution in which a specific compliance mechanism is engaged with the holding member while a contact pressure is applied thereto by a contact pressure applying unit (for example, refer to Patent Documents 1 and 2).
As a unit for forming the contact terminals and lead-out wires, there is a technique of forming molds for the formation of the contact terminals by anisotropic etching of a silicon wafer, forming the contact terminals and lead-out wires by using the molds, and then removing the silicon wafer molds after the formation of the contact terminals and lead-out wires (for example, refer to Patent Documents 3 and 4).
Patent Document 1: Japanese Patent Application Laid-Open No. Hei 11(1999)-23615
Patent Document 2: Japanese Patent Application Laid-Open No. Hei 10(1998)-308423
Patent Document 3: Japanese Patent Application Laid-Open No. Hei 11(1999)-97471
Patent Document 4: Japanese Patent Application Laid-Open No. Hei 7(1995)-283280